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Can I Add External SRAM to My A7 Design? Although the A7 directly supports low-cost, high-performance SDRAM, some applications require an external SRAM interface. This article describes how to build such an interface.
In this example, assume that the application has 2Mx32 of Flash for code and configuration storage and 8Mx32 of SRAM, as shown in Table 1. Both the Flash and SRAM interfaces are built from four byte-wide devices. Table 1. Memory Connected to A7 Example Design.
Figure 1 shows the connections between the A7S device and the external Flash and SRAM. The Flash devices connect directly to the A7’s memory interface unit (MIU) signal. The SRAM interface shares a majority of signals, including the address, data, output enable, and write-enable signals. The only unique signals between the Flash and SRAM are the chip-enable signals.
Figure 1. An example A7 interface to both external Flash and external SRAM. The four byte-wide Flash devices are separately enabled using the A7’s dedicated CE3- through CE0- outputs. These four enables allow byte, half-word, and word-wide transactions to the Flash. The timing for Flash transactions is controlled by the MIU itself. When you select a specific Flash device and speed grade during configuration, FastChip automatically configures the MIU timing for you. The four byte-wide SRAM devices are separately enable, but using logic created in the CSL matrix. In specific, the Chip Select soft IP module provides a convenient way to create the individual chip-enable outputs. Using the Set it to External memory space option, the SRAM devices can share most of the MIU’s signals. However, the memory access timing is controlled by the other CSL logic. Let’s build the interface.
In this example, assume that the SRAM requires four clock cycles for each access. Because we need at least one wait-state to meet this requirement, check Insert initial wait-state. The additional two wait-states will be added later using another soft IP module.
For SRAM_CE3-, we want this Chip Select module to respond to all transactions that require byte lane B3. Set Lane Sensitivity to LANEB3. As shown in Table 2, this Chip Select module with then respond to all word-wide transactions, all transactions to the high half-word, and all transactions by byte-lane 3. Click OK when finished. Table 2. Byte Lanes and Response to Various Transaction Sizes.
Choose the Wait Control v.2 module from the FastChip library. Type WAIT_CE3 for the Component Name. Connect the “waitreq” wait request input to the output of the chip select module by typing SRAM_CE3_ or choosing the signal from FastChip’s Connection Port chooser.
Whenever a bus master addresses the associated Chip Select module, the module will insert an initial wait-state followed by two additional wait-states inserted by Wait Control module, for a total period of four CSI bus cycles.
The outputs from the Chip Select modules are active-High. The external memory requires an active-Low signal. Connect the outputs from the Chip Select modules to the Output module. Invert each signal by prepending the signal name with a tilde (~), indicating that the signal is inverted. The Out port of the module expects four signals. Type {~SRAM_CE3_,~SRAM_CE2,~SRAM_CE1,~SRAM_CE0} to create a four-signal connection, inverting each of the signals.
Set the data width for the MIU interface to 2Mx32. This action reserves the proper number of address, data, and control signals on the A7 device. Again, the data width of the external Flash and SRAM memory interfaces must be identical.
Click SDRAM Memory. Set the number of external banks to 0. Set the Depth x Width of the SDRAM interface to None. Click OK when finished.
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Start FastChip and choose a Chip Select v.4 module from
FastChip’s soft IP module library. Type 
Click Properties and type 
Assign the address region for the SRAM interface. In this example,
assume that the SRAM occupies the 8Mbyte region between 0x2000_0000 and
0x2100_0000. To specify this region, click Advanced Addressing under
Addressing Mode. Type in the starting CSI address as 
Repeat Steps 1 through 3 to create similar logic for SRAM_CE2-,
SRAM_CE1-, and SRAM_CE0-. Be sure to set the proper byte lane sensitivity.
In this example, the SRAM requires four clock cycles per access,
requiring three wait-states on the CSI bus during a transaction. The Chip
Select module asserts the first wait-state whenever it is addressed over the
bus. Checking the Insert initial wait-state causes this initial
wait-state. A separate soft IP module asserts the two additional wait-states
required.
Click Properties and set the number of additional wait-states
to 2. Click OK when finished.
Each Chip Select module requires a corresponding wait-state
generator. Repeat Steps 5 and 6 for the other chip select signals.
Connect the chip-select signals to associated output pins. Select an
Output v.2 module from the FastChip library. Type 
Click Properties. Set the Output Buffer Slew Rate Control to Fast
to minimize the chip select delay. If the design will operate in power-down
mode, select Output active during power-down to pull the SRAM’s CE# pins
High to prevent spurious reads or writes. Click OK when finished.
Invoke
the I/O Editor either by selecting Constraints 
Click
the MIU button from the I/O Editor toolbar.
Because
both the Flash and SRAM interfaces are 32-bit wide, but use byte-wide memory
devices, enable all four chip-enable signals by checking CEN[1], CEN[2],
and CEN[3].
If
adding an external SRAM, be sure to disable the SDRAM memory interface. The
extra loading of the SRAM devices on the MIU interface may violate the timing
requirements for an SDRAM interface. Do not use both an external SRAM and
external SDRAM interface in the same application.
